Instruction Cycle
A program residing in the memory unit of the computer consists of a sequence of instructions. The program is executed in the computer by going through a cycle for each instruction. Each instruction cycle in turn is subdivided into a sequence of subcycles or phases. In the basic computer each instruction cycle consists of the following phases:
- Fetch an instruction from memory.
- Decode the instruction.
- Read the effective address from memory if the instruction has an indirect address.
- Execute the instruction.
Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the next instruction. This process continues indefinitely unless a HALT instruction is encountered.
Frequently Asked Questions
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Ans: The last three waveforms in Fig. 5-7 show how SC is cleared when
D3T4 = I. Output D3 from the operation decoder becomes active at the end of
timing signal T2• When timing signal T4 becomes active, the output of the AND
gate that implements the control function D3T4 becomes active. This signal is
applied to the CLR input of SC. view more..
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Ans: The timing for all registers in the basic computer is controlled by a master clock
generator. The clock pulses are applied to all flip-flops and registers in the
system, including the flip-flops and registers in the control unit. The clock
pulses do not change the state of a register unless the register is enabled by view more..
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Ans: Before investigating the operations performed by the instructions, let us discuss
the type of instructions that must be included in a computer. A computer
should have a set of instructions so that the user can construct machine
language programs to evaluate any function that is known to be computable.
The set of instructions are said to be complete if the computer includes a
sufficient number of instructions in each of the following categories: view more..
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Ans: A program residing in the memory unit of the computer consists of a sequence
of instructions. The program is executed in the computer by going through a
cycle for each instruction. Each instruction cycle in turn is subdivided into a
sequence of subcycles or phases. In the basic computer each instruction cycle
consists of the following phases: view more..
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Ans: Initially, the program counter PC is loaded with the address of the first instruction
in the program. The sequence counter SC is cleared to 0, providing a
decoded timing signal To. After each clock pulse, SC is incremented by one,
so that the timing signals go through a sequence T0, T1, T2, and so on. The
rnicrooperations for the fetch and decode phases can be specified by the
following register transfer statements. view more..
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Ans: The timing signal that is active after the decoding is T3• During time T,, the
control unit determines the type of instruction that was just read from memory.
The flowchart of Fig. 5-9 presents an initial configuration for the instruction
cycle and shows how the control determines the instruction type after the
decoding. The three possible instruction types available in the basic computer
are specified in Fig. 5-5. view more..
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Ans: Register-reference instructions are recognized by the control when 07 = 1 and
I = 0. These instructions use bits 0 through 11 of the instruction code to specify
one of 12 instructions. These 12 bits are available in IR(0-11). They were also
transferred to AR during time T2• view more..
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Ans: In order to specify the rnicrooperations needed for the execution of each
instruction, it is necessary that the function that they are intended to perform
be defined precisely. Looking back to Table 5-2, where the instructions are
listed, we find that some instructions have an ambiguous description. This is
because the explanation of an instruction in words is usually lengthy, and not
enough space is available in the table for such a lengthy explanation. We will
now show that the function of the memory-reference instructions can be
defined precisely by means of register transfer notation. view more..
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Ans: This is an instruction that performs the AND logic operation on pairs of bits
in AC and the memory word specified by the effective address. The result of view more..
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Ans: This instruction adds the content of the memory word specified by the effective
address to the value of AC. The sum is transferred into AC and the output carry
C,., is transferred to the E (extended accumulator) flip-flop. The rnicrooperations
needed to execute this instruction are view more..
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Ans: This instruction transfers the memory word specified by the effective address
to AC. The rnicrooperations needed to execute this instruction are
view more..
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Ans: This instruction stores the content of AC into the memory word specified by
the effective address. Since the output of AC is applied to the bus and the data
input of memory is connected to the bus, we can execute this instruction with
one microoperation: view more..
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Ans: This instruction is useful for branching to a portion of the program called a
subroutine or procedure. When executed, the BSA instruction stores the address
of the next instruction in sequence (which is available in PC) into a
memory location specified by the effective address. The effective address plus
one is then transferred to PC to serve as the address of the first instruction in
the subroutine. This operation was specified in Table 5-4 with the following
register transfer: view more..
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Ans: The BSA instruction performs the function usually referred to as a subroutine
call. The indirect BUN instruction at the end of the subroutine performs
the function referred to as a subroutine return. In most commercial computers,
the return address associated with a subroutine is stored in either a processor view more..
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Ans: This instruction increments the word specified by the effective address, and
if the incremented value is equal to 0, PC is incremented by 1. The programmer
usually stores a negative number (in 2's complement) in the memory word. As
this negative number is repeatedly incremented by one, it eventually reaches
the value of zero. At that time PC is incremented by one in order to skip the
next instruction in the program. view more..
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Ans: A computer can serve no useful purpose unless it communicates with the
external environment. Instructions and data stored in memory must come
from some input device. Computational results must be transmitted to the user
through some output device. Commercial computers include many types of view more..
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Ans: The input register INPR consists of eight bits and holds an alphanumeric
input information. The 1-bit input flag FGI is a control flip-flop. The flag bit is view more..
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Ans: The final flowchart of the instruction cycle, including the interrupt cycle for the
basic computer, is shown in Fig. 5-15. The interrupt flip-flop R may be set at
any time during the indirect or execute phases. Control returns to timing signal
T0 after SC is cleared to 0. If R = 1, the computer goes through an interrupt
cycle. If R = 0, the computer goes through an instruction cycle. view more..
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