Control of Registers and Memory




The registers of the computer connected to a common bus system are shown in Fig. 5-4. The control inputs of the registers are LD (load), INR (increment), and CLR (clear). Suppose that we want to derive the gate structure associated with the control inputs of AR. We scan Table 5-6 to find all the statements that change the content of AR

R 'T0: AR +- PC

R'T2: AR +-IR(0-1 1)

D7IT3: AR +-M[AR]

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RT0: AR +-0 D5T4: AR +-AR + 1

The first three statements specify transfer of information from a register or memory to AR . The content of the source register or memory is placed on

the bus and the content of the bus is transferred into AR by enabling its LD control input. The fourth statement clears AR to 0. The last statement increments AR by 1. The control functions can be combined into three Boolean expressions as follows:

LD(AR) = R'To + R'T, + D;

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IT, CLR(AR) = RTo

INR(AR) = D5T,

where LD(AR) is the load input of AR, CLR(AR) is the clear input of AR, and INR(AR) is the increment input of AR . The control gate logic associated with AR is shown in Fig. 5-16.

Control of Registers and Memory

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Frequently Asked Questions

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Ans: he block diagram of the control logic gates is shown in Fig. 5-6. The inputs to this circuit come from the two decoders, the I flip-flop, and bits 0 through 11 of IR. The other inputs to the control logic are: AC bits 0 through 15 to check if AC = 0 and to detect the sign bit in AC( view more..
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Ans: 1. A memory unit with 4096 words of 16 bits each 2. Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC 3. Seven flip-flops: I, S, E, R, lEN, FGI, and FGO 4. Two decoders: a 3 x 8 operation decoder and a 4 x 16 timing decoder view more..
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Ans: The final flowchart of the instruction cycle, including the interrupt cycle for the basic computer, is shown in Fig. 5-15. The interrupt flip-flop R may be set at any time during the indirect or execute phases. Control returns to timing signal T0 after SC is cleared to 0. If R = 1, the computer goes through an interrupt cycle. If R = 0, the computer goes through an instruction cycle. view more..
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Ans: The registers of the computer connected to a common bus system are shown in Fig. 5-4. The control inputs of the registers are LD (load), INR (increment), and CLR (clear). Suppose that we want to derive the gate structure associated with the control inputs of AR. We scan Table 5-6 to find all the statements that change the content of AR view more..
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Ans: The control gates for the seven flip-flops can be determined in a similar manner. For example, Table 5-6 shows that lEN may change as a result of the two instructions ION and !OF. view more..
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Ans: The 16-bit common bus shown in Fig. 5-4 is controlled by the selection inputs S2, S1, and 50• The decimal number shown with each bus input specifies the equivalent binary number that must be applied to the selection inputs in order to select the corresponding register. Table 5-7 specifies the binary numbers for S2S1S0 that select each register. Each binary number is associated with a Boolean variable x1 through x7, corresponding to the gate structure that must be active in order to select the register or memory for the bus. view more..




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