8085 Microprocessor Instructions




An instruction can be defined as a command issued in the form of a binary pattern to perform the assigned task on a specified data. Group of instructions is known as instruction set which decides the function of microprocessor. Each instruction consist of two parts: first part is called OPCODE and the second as OPERAND. Opcode specifies the function to be performed and operand provides the data to be operated on.

Addressing modes of 8085 -

The way operand is specified in instruction is called addressing mode. 8085 has following addressing modes:

  1. Immediate addressing :- In this mode, 8 or 16 bit data is specified in the instruction itself as its one of the operands. Normally, instructions have "I" in their mnemonics. Eg: MVI A,33H.
  2. Register addressing :- In this mode, operands are microprocessors registers only i.e. operations is performed within various registers. Eg: MOV C,B.
  3. Direct addressing :- In this mode, one of the operands is data stored in memory. The memory address of operand (data) is directly given in instruction itself. Eg: STA 3050H.
  4. Indirect addressing :- In this mode, one of the operands is data stored in memory. The memory address of operand (data) is specified by register pair. Eg: LDAX D.
  5. Implied/ Inherent/ Implicit addressing :- This mode does not require any operand, the data is specified by opcode itself. Eg: CMP.

8085 microprocessor instruction set has 74 operation codes that result in 246 instructions. 8085 instructions can be classified into following five functional groups:

1. Data Transfer/ Copy Operations - These types of instructions transfer data from source to destination, without modifying the contents of the source. Data Transfer can take place between registers, between a memory location and a register, between an I/O device and accumulator.

  • MOV : This instruction copies content of source register (Rs) into destination register (Rd). The contents of source register are not altered. If one of operand is memory location, its location is specified by contents of HL pair. Eg: MOV A,B.
  • MVI : The 8 bit data is stored in destination register or memory. Eg: MVI B,57H.
  • LDA : It is called load accumulator. The content of memory location specified by 16 bit address in operand are copied to accumulator. The contents of source are not altered. Eg: LDA 2014.
  • LXI : It is called load register pair immediate. It loads 16 bit data in register pair designated in operand. Eg: LXI H,2034.
  • LDAX : It is load accumulator indirect. The contents of register pair points to a memory location. This instruction copies contents of memory location to accumulator. The contents of either register pair or memory are not altered. Eg: LDAX BC.
  • LHLD : It is load H&L registers directly. The instruction copies the content of memory location pointed by 16-bit address into register L and copies content of next memory location into register H. The contents of source memory are not altered. Eg: LHLD 2040.
  • STA : It is store Accumulator Direct. The contents of accumulator are copied into memory location specified by operand. Eg: STA 4350H.
  • STAX : It is store Accumulator Indirect. The contents of accumulator are copied into memory location specified by contents of operand. Eg: STAX B.
  • SHLD : Store HL pair directly. The contents of register L are stored into memory location specified by 16 bit address and contents of register H are stored in next memory location. Eg: SHLD 2470.
  • XCHG : Exchange H&L with D&E. The contents of H are exchanged with contents of register D and contents of register L are exchanged with contents of register E. Eg: XCHG.

2. Arithmetic Operations - These instructions are responsible for performing arithmetic operations like addition, subtraction, increment and decrement. Addition includes addition between any 8 bit numbers / the contents of register / the contents of memory location and contents of accumulator and the sum will be stored in accumulator. Same process is done in case of subtraction. Increment/ Decrement means 8 bit number/ contents of a register or a memory location can be incremented/ decremented by one and same is the case with 16 bits contents of register pair.

  • ADD : The contents of operand (register or memory) are added to contents of accumulator. All flags are modified to reflect the result of addition. Eg: ADD B.
  • ADC : The contents of operand & carry flag are added to contents of accumulator and result is stored in accumulator. Eg: ADC B.
  • ADI : It is Add immediate to Accumulator. The 8 bit data (operand) is added to contents of accumulator and the result is stored in accumulator. Eg: ADI 45.
  • ACI : The 8 bit data and carry flag are added to contents of accumulator and result is stored in accumulator itself. Eg: ACI 45.
  • DAD : The 16 bit contents of specified register pair are added to contents of HL pair and the sum is stored in HL register pair. If result is greater than 16 bit, carry flag is set and no other flags are modified. Eg: DAD B.
  • SUB : The contents of operand (register or memory) are subtracted from accumulator. If operand is memory, its location is specified by contents of HL register pair. All flags are modified. (Common to all) Eg: SUB M.
  • SBB : The contents of operand and borrow flag are subtracted from contents of accumulator. Eg: SBB C.
  • SUI : 8 bit data is subtracted from contents of accumulator. Eg: SUI 45.
  • SBI : The 8 bit data and borrow flag are subtracted from contents of accumulator and result is stored in accumulator. Eg: SBI 45.
  • INR : The contents of designated register or memory are incremented by 1. Result is stored in same place. Eg: INR B.
  • INX : The contents of designated register is incremented by 1. Result is stored in same place. Eg: INX B.
  • DCR : The contents of designated register or memory are decremented by 1. Result is stored in same place. Eg: DCR C.
  • DCX : The contents of designated register is decremented by 1. Result is stored in same place. Eg: DCX B.
  • DAA : It is Decimal Adjust Accumulator. The contents of accumulator are changed from a binary value to two 4 bit BCD digit. It uses auxiliary flag to perform BCD conversion. All flags are modified. If value of lower order 4 bits in accumulator is greater than 9 or if Auxiliary Carry is set, the instruction adds 6 to lower order 4 bit.

 

3. Logical Operations - These type of instructions are used for performing logical operations like AND, OR, EX-OR, rotate, compare and complement with the contents of accumulator. Results are stored in accumulator.

  • CMP : Compare contents of register or memory with accumulator by performing subtraction. Eg: CMP B.
  • CPI : Compare immediate data with accumulator. Eg: CPI 45.
  • ANA : Logical AND register or memory with accumulator. Eg: ANA B.
  • ANI : Logically AND the contents of accumulator & 8 bit data and result is stored in accumulator. Eg: ANI 24.
  • XRA : Exclusive OR the contents of memory or register with accumulator. All flags are modified and CY, AC are reset. Eg: XRA B.
  • XRI : 8 bit data/ operand is exclusicve ORed with accumulator and stored in accumulator. Eg: XRI 45.
  • ORA : Logically ORed contents of accumulator with register or memory. All flags are modified. Eg: ORA M.
  • ORI : Logically ORed 8 bit data with contents of accumulator. Eg: ORI 45.
  • RLC : Each bit of accumulator is rotated left by one position. CY is modified according to bit D7 and remaining not affected.
  • RRC : Each bit of accumulator is rotated right by one position. CY is modified according to bit D0 and remaining not affected.
  • RAL : Each bit of accumulator is rotated left through carry flag. Bit D7 is placed in carry flag and carry flag is placed at D0. Remaining flag are not modified.
  • RAR : Each bit of accumulator is rotated right through carry flag. Bit D0 is placed in carry flag and carry flag is placed at D7. Remaining flag are not modified.
  • CMA : The contents of accumulator are complemented. This means 0 is changed to 1 or vice-versa.
  • CMC : The contents of carry flag are complemented. This means reset(0)-> set(1).
  • STC : The carry flag is set to 1 & remaining are unaffected.

 

4. Branching Control Operations - These types of instructions can change the sequence of program either conditionally or unconditionally. Conditional instructions can make the program to jump to that particular memory location if condition is satisfied while unconditional instructions will always make the program to jump as soon as the instruction arrives.

  • JMP : It is Jump Unconditionally. The program sequence is transferred to memory location specified by 16 bit address. Eg: JMP 2034.
  • Jump Conditionally : These are JC (jump on carry), JNC (jump on no carry, CY=0), JP (jump on positive, S=0), JM (jump on negative, S=1), JZ (jump on zero, Z=1), JNZ (jump on no zero, Z=0), JPE (jump on parity even, P=1), JPO (jump on parity odd, P=0). Eg: JC2043
  • CALL : It in Unconditional subroutine call. The program sequence is transferred to memory location specified by 16 bit address. Before the transfer, the address of next instruction after CALL is stored/pushed into stack. Eg: CALL 2034.
  • Call Conditionally : These are CC, CNC, CP, CM, CZ, CNZ, CPE, CPO. Eg: CC 2034.
  • RET : Return from subroutine unconditionally
  • Return Conditionally : These are RC, RNC, RP, RM, RZ, RNZ, RPE, RPO.

 

5. Stack, I/O & Machine Control Operations - These instructions communicate with Input/ Output Ports and control machine functions such as Halt, Interrupt, or do nothing. In this port address of Input & Output devices are exchanged with accumulator.

  • IN : Input data to accumulator from port with 8 bit address. The contents of input port designated by 8 bit address (operand) are read and loaded into accumulator. Eg: IN 82.
  • OUT : Output data from accumulator to port with 8 bit address. Contents of accumulator are copied into I/O port specified by operand. Eg: OUT 87.
  • SPHL : It copies HL registers to stack pointers. The instruction loads of contents of H & L register into stack pointer register. H to higher order address and L to lower order address.
  • XTHL : The contents of L register are exchanged with stack location pointed out by contents of stack pointer register. The contents of H register are exchanged with next stack location. The contents of source register are not altered.
  • PUSH : The contents of register pair are copied onto stack. The stack pointer is decremented & contents of higher order register are copied onto that location. The stack pointer is decremented by 1 and contents of lower order register are copied to that location. Eg: PUSH B.
  • POP : The contents of memory location pointed out by stack pointer register are copied to lower order register. The stack pointer is incremented by 1 & contents of that memory location are copied to higher order register. The stack pointer is again incremented by 1. Eg: POP H.

Programming is taught using these instructions and addressing modes. Subroutine is also studied. Subroutine is a group of instructions that performs a subtask (e.g.: time delay or arithmetic operations) of repeated occurrence. This unit can then be used in programs wherever that particular task have to be performed. A subroutine is often coded so that it can be called several times & then branch back to next instruction after call once the subroutine's task is done.

Counters are designed by loading an appropriate number into one of the registers and using increment or decrement instructions (INR / DCR) loop is being continued. It count number of electrical pulses. To count certain events electrical pulses is proportional to number of events generated for counting.

Time delays are used in setting up accurate timing between two events. A time delay is designed by using a register which is loaded with a number or delay count, depending on the time delay required and setting a loop with a conditional jump instruction to decrease the count until it reaches zero.



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