8086 Microprocessor Architecture and Instruction Set
8086 microprocessor is a 16 bit microprocessor i.e. its mostly operations are designed to work with 16 bit binary words.
PIN DIAGRAM of 8086 :
It is 40 pin I.C.
It has 16 bit data bus and 20 bit address bus. It can perform bit, byte, word and string with arithmetic and logical operations.
It operates in two modes:
1. Maximum mode
2. Minimum mode
- • Pin 1,20 (GND) : Connected to ground.
- • Pin 2-16 (AD14-AD0), Pin 39 (AD15) : It is Address/ Data Bus. It is bidirectional Input/ Output. Both address/data bus exist in Time Multiplexed Mode.
- • Pin 17 (NMI) : It is Non-Maskable Interrupt reque
- • Pin 18 (INTR) : It is interrupt control signal. It is level triggered interrupt request. It is used for hardware interrupt.
- • Pin 19 (CLK) : It is clock input. It is used for basic timing for various operation.
- • Pin 21 (RESET) : When it is high it causes microprocessor to terminate current activity and start execution from FFFF0H.
- • Pin 22 (READY) : It is active high input signal from slow devices to inform the mp that they have completed data transfer.
- • Pin 23 (TEST) : It is unidiirectional control input signal. It is examined by WAIT instruction. If it is 1 then WAIT instruction waits for TEST to become 0.
- • Pin 24,25 (QS1,QS0) : It is Queue Status signal. It is output signal. It reflect the status of instruction queue in previous clock cycle. QS0 QS1 Status 0 0 No operation 0 1 First byte of opcode from the queue 1 0 Empty the queue 1 1 Subsequent byte from the queue
- • Pin 26-28 (S0-S2) : It is status line which indicate type of operation. S2 S1 S0 CHARACTERISTICS 0 0 0 Interrupt acknowledge 0 0 1 Read I/O port 0 1 0 Write I/O port 0 1 1 Halt 1 0 0 Code access 1 0 1 Read memory 1 1 0 Write memory 1 1 1 Passive state
- • Pin 29 (LOCK) : It is input signal. It lock peripherals off the system.
- • Pin 30-31 (RQ/ GT 0-1) : It is Bus Request/ Grant signal. It indicate function of current bus cycle. It is similar to HOLD & HLDA.
- • Pin 32 (RD) : It is read signal. The data bus is receptive to data from memory I/ O devices.
- • Pin 33 (MN/MX) : It is Minimum/Maximum mode. If it is high, then mp is in minimum mode operation. If it is low, then mp is in maximum mode.
- • Pin 34 (BHE/S7) : It is Bus High Enable/Status. It enables most significant data bus bit during read/write.
- • Pin 35-38 (A19-16, S6-3) : It is Address/Status bus. It is unidirectional output bus. A17/S4 A16/S3 FUNCTION 0 0 Extra segment access 0 1 Stack segment access 1 0 Code segment access 1 1 Data segment access
- • Pin 40 (Vcc) : Connected to +5V DC.
1. INTA : It is Interrupt Acknowledgement output pin. It indicate interrupt request is recognized.
2. HOLD : It is input control signal. Microprocessor gives up control of buses to DMA controller.
3. HLDA : It is Hold Acknowledgement signal. If it is high, it indicate that request is granted.
4. ALE : It is Address Latch Enable control signal. It is output signal.
5. DEN : It is Data Enable control signal. It activate external data bus buffer.
6. DT/R : It is Data Transmit/Receive control signal. If it is high, processor transmit the data. If it is low, processor receive the data.
7. M/IO : It is Memory/ Input-Output control signal. If it is high, then data transfer occurs from memory otherwise from input-output device.
8. WR : It is write control signal. If it is low then data write into memory or I/O device & memory bus contains valid address. It supports multiprogramming. It use pipelining concept so that it can fetch up to six instruction bytes from memory and store in a queue.
Architecture of 8086 :
8086 microprocessor is divided into two independent function parts:
1. Bus Interface Unit (BIU)
2. Execution Unit (EU)
The above both unit work simultaneously for faster speed and increase the number of instruction executed per unit time.
1. Bus Interface Unit (BIU) - It provides 16 bit data bus and 20 bit address bus. It is responsible for all external bus operation which are instruction fetch, instruction queuing, operand fetch & storage, address relocation and bus control. BIU uses a mechanism known as instruction stream queue to implement pipeline architecture. This queue permits prefetch of upto six bytes of instruction code. With its 16 bit data bus, the BIU fetches 2 instruction bytes in a single memory cycle. EU access the queue from operand. It reads one instruction byte after the other from output of queue. If BIU is already fetching an instruction when EU request it to read or write operands, the BIU first completes the instruction fetch bus cycle initiating the operand read/write cycle.
2. Execution Unit (EU) - It is responsible for decoding and executing instruction. EU extracts instruction from top of queue, decodes them, generate operands, passes them to BIU & requests it to perform read or write operation and perform operation specified by instruction. EU tests status and control flags and update them based on results. If queue is empty, EU waits for next instruction byte to be fetched and shifted to top of queue.
Apart from brief study of pin diagram and architecture, there are also various topics. These include:
• Flag register - In 8086 microprocessor there are total 9 flags. Five flags are common to 8085. Overflow (set if result is out of range), Trap (set if a trap is executed), Interrupt (set if interrupt is recognized) and Direction flag (set if string is proceed from higher address to lower address) are also there.
• Memory segmentation - Dividing the whole 1 MB memory of 8086 microprocessor in segments (each 64 kB) is named as memory segmentation. It has following advantages:
1. 8086 microprocessor has to manipulate and store only 16 bit address instead of 20 bit.
2. Faster & easier searching & accessing of memory location.
3. Since data is stored in different area of memory each time the programmed is executed it can be relocated.
• Operating modes - The operating modes of 8086 microprocessor are determined by logic level applied to the input. There are of two types: Minimum mode and Maximum mode.
• Addressing mode - 8086 has various addressing modes. Some of them are Register addressing mode, immediate addressing mode, Direct addressing mode, Implicit addressing mode (same as in 8085).
• Register indirect addressing mode :- In this mode, the memory offset address can be specified by two base register and two index register. Eg: MOV AX,[BX].
• Index indirect addressing mode :- In this mode, the memory offset address can be specified by two index register (SI & DI) with 8 or 16 bit displacement. Eg: MOV CL, [SI + 03H].
• Based indirect addressing mode :- In this mode, the memory offset address can be specified by any two based register with 8 or 16 bit displacement and base address is given by SS instead of DS. Eg: MOV DL, [BP-02H].
• Based and Index indirect addressing mode :- In this mode, pair of base (BX/BP) and index (SI/DI) is used to specify address. MOV AX, [BP+SI].
• Instruction Set - 8086 has 9 instruction (mostly same as in 8085) which are:
1. Data Copy/Transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Shift and rotate instructions
5. Branch instructions
6. Loop instructions
7. Flag (Bit) Manipulation instructions
8. Processor Control instructions
9. String instructions