8085 Microprocessor Interfacing
This unit consists of study of various microprocessor chips along with their pin description, architectural diagram, their features and their applications.
- 8259 (Programmer Interrupt Controller) - It is a 28 pin I.C. including pins related to data bus, buffer, three registers (IRR, ISR and IMR), cascade buffer (cas 0, cas 1, and cas 2), priority resolver, control logic and Read/ Write logic. 8259 can work in fully nested mode, automatic rotation and specific rotation mode.
- CS: Chip Select. This signal enables the chip to perform various functions.
- WR: It is active low signal. When signal is low, 8259 accepts command word from microprocessor.
- RD: It is active low signal. When signal on this pin is low, 8259 sends various status on the data bus for processor.
- D0-D7: It is bidirectional data bus.
- CAS0-CAS2: These are cascade lines.
- INT: This line is used to interrupt microprocessor.
- INTA: Interrupt Acknowledgement
- IR0-IR7: These lines are used for interrupt requests.
- A0: This address line acts in conjunction with RD, WR, CS to interrupt command words CPU writes and status the CPU wants to read.
- 8257 (DMA Controller) - Direct Memory Access (DMA) is an I/O technique commonly used for high-speed data transfer. In DMA transfer scheme, data are directly transferred from I/O devices to RAM or from RAM to I/O device. The Intel 8257 is a programmable DMA controller. It is a 4-channel programmable direct memory access controller. It is a 40-pin I.C. package and requires a single +5V supply for its operation and allows up to four I/O devices to be interfaced to the microprocessor.
- Data Bus (D0-D7): These are bi-directional tri-state signals connected to the system data bus. During DMA cycles these lines are used to send the most significant bytes of the memory address from one of the DMA address registers.
- Address Bus (A0-A3 and A4-A7): The most least significant lines A0-A3 are bi-directional tri-state signals. A4-A7 are unidirectional lines, provide 4-bits of address during DMA service.
- Address Strobe (ADSTB): This signal is used to demultiplex higher byte address and data using external latch.
- Address Enable (AEN): This is active high signal enables the 8-bit latch containing the upper 8- address bit onto the system address bus.
- Memory Read & Write (MEMR ,MEMW): These are active low tri-state signals. The MEMR signal is used to access the data while MEMW is used to write data to addressed memory location.
- I/O Read & Write (IOR&IOW): These are active low bi-directional signals.In the active cycle, IOR signal is used to access data from peripheral and IOW signal is used to send data from the peripheral.
- Chip Select(CS): This is an active low input, used to select 8257 as an I/O device during the idle cycle.
- RESET: This active high signal clear the command status, request and temporary registers. After reset, device is in idle cycle.
- Ready: This input is used to extend the memory read and write signals from 8257.
- HOLD Acknowledgement (HLDA): This active high signal indicates that it has relinguished control of the system bus.
- DREQ0-DREQ3: These are DMA request lines, which are activated to obtain DMA service, until the corresponding DACK signal goes active.
- DACK0-DACK3: These are used to indicate peripheral devices that DMA request is granted.
- Terminal Count(TC): This is active high signal concern with the completion of DMA service.
- Mark: This output notifies the selected peripheral that current DMA cycle is 128th cycle since previous MARK output.
- 8255 (Programmable Peripheral Interface) - 8255 also known as PPI is widely used, programmable, parallel I/O device. It is an important general purpose I/O device that can be used with almost any microprocessor. It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O. It is economical and flexible and can be used when multiple I/O ports are required. 8255 has 24 I/O pins that can be divided into 3 ports each of 8 pins. These ports are two 8-bit parallel ports A and B and third port C with remaining eight ports.
- Data Bus(D0-D7): These bi-directional, tri-state data bus lines are connected to the system data bus. They are used to transfer data and control word from microprocessor.
- Port A(PA0-PA7): These 8-bit bi-directional I/O pins are used to send data to output device and the receive data from input device.
- Port B(PB0-PB7): These 8-bit bi-directional I/O pins are used to send data to output device and to receive data from input device.
- PC0-PC7: These 8-bit bi-directional I/O pins are divided into two groups PC0-PC3 & PC7-PC4. These groups individually can transfer data in or out.
- RD: When this pin is low, the CPU can read the data in the ports or the status word, through the data buffer.
- WR: When this pin is low, the CPU can write data onto ports or onto the control register through the data bus buffer.
- CS: This is an active low input which can be enabled for data transfer operation.
- RESET: This is an active high input used to reset
- A0,A1: These input signals control the selection of the control 1 status word registers or one of the three ports.
- 8253/8254 (Programmable Interval Timer) - A programmable counter/timer is used in real time application for timing and counting function such as BCD/ binary counting, generation of accurate time delay, generation of square wave of desired frequency, rate generation etc. 8253 and 8254 are popular programmable interval timer chips. 8254 is an upgraded version of 8253, and both of these are pin-compatible. 8254 includes status read-back command which helps in reading count by microprocessor while the counter is decrementing.
- Data Bus Buffer: This tri-state, bi-directional, 8-bit buffer is used to interface 8253/54 to the system data bus.
- Read/Write Logic: It has 5 signals-RD, WR, CS, A0 &A1. In the peripheral I/O mode, the RD and WR signals are connected to IOR and IOW respectively. The control word register and counters are selected according to signals on lines A0 and A1.
- Control Word Registers: This register is accessed when lines A0 and A1 are at logic 1. It is used to write a command word which specifies the counter to be used, its mode and either read or write operation.
- Counters: These three functional blocks are identical in operation. Each counter is a 16 bit presuitable down counter. The counter can operate in either binary or BCD and its input, gate and output are configured by the selected mode stored in control word register.
- Modes of Operation: The 8254 can operate in six different modes and the gate of a counter is used either to disable or enable counting. The modes are Interrupt on terminal count, Hardware- retriggerable one-shot, Rate generator, Square wave generator, Software-triggered strobe, Hardware-triggered strobe.
- 8155 (Multipurpose Programmable Device) - It is programmable interface device used to interface a I/O device to the microprocessor. It is a multifunction device designed to use in minimum mode system. It contains RAM, I/O ports and timer. It is designed to be compatible with 8085. It includes 256 bytes of read/write memory and a 14-bit timer.
- Control Logic: It is specially designed to eliminate the need for external demultiplexing of lines AD7- AD0 and generating seperate control signals for memory and I/O.
- Chip Enable(CE): This is an active low input which must be enabled for the data transfer operation between CPU and 8155.
- I/O Memory Select(IO/M): This pin selects either the five registers (Command status, PA0-PA7, PB0- PB7, PC0-PC5) or the memory portion.
- ALE: It is used to latch the lower 8-bit address A7-A0 in the internal latch.
- Read(RD): When this pin is low, the CPU can read the data from ports, registers and the memory.
- Write(WR): When this pin is low, the CPU can write the data into ports, registers and the memory.
- Reset: When this pin is high, the control register is cleared, all the ports are set to the simple input, mode and timer is stopped.
- Address/Data Bus: The tri-state Address/Data lines are connected to the CPU. The 8-bit address is latched into the internal latch of 8155 on the falling edge of ALE. The address can be either for the memory section or for the I/O section depending on the IO/M.
- Timer Clock: This signal is a clock input for the internal 14 bit binary down counter.
- Timer Out: This is activated when the counter value is zero.
- 8279 (Programmable Keyboard/Display Interface) - 8279 is an approach to interface a matrix keyboard and a multiplexed display. It is a 16 pin device with two sections: Keyboard and Display. It has single 16 character display and dual 8 or 16 numerical display. It has simultaneous keyboard display operations. It has scanned sensor mode and programmable scan timing. It is single 16 character display. Keyboard segment is connected to a 64 content key matrix. A 16*8 Read or Write memory is used to read available information for display purpose. 8279 is a 40 pin device. It is divided into four functional groups as CPU interface, Key data, Display data, Scan.
- DB0-DB7: It is bi-directional data bus. All data, commands and status information between CPU and 8279 are transmitted on these bidirectional 8-bit data bus.
- RD: It is an active low signal. When it is low, CPU tends the contents of selected register from 8279 depending on the type of command and the status of A0 signal.
- WR: It is an active low signal. When WR is low, CPU loads the data into selected register (control or display register) depending on the status of A0 signal.
- A0: When A0 is high, signals are interpreted as a command or status. When it is low, signals are interpreted as data.
- CS: Chip Select (CS) is an active low signal. When it is low, it enables the communication between CPU and 8279.
- Reset: A high signal on this pin resets 8279. After being reset, 8279 is configured in sixteen 8-bit character display left entry or encoded scan keyboard 2 key lockout or the program clock prescaler is set to 31.
- CLK: This signal is usually driven by the system clock and used to generate internal timings.
- IRQ: This signal is used to implement interrupt driven input system. In scanned keyboard mode, the interrupt line goes low when there is data in the FIFO sensor RAM. The interrupt line goes low with each FIFO sensor, RAM reads and returns high if there is still information in the RAM.
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