Timing and Control
The timing for all registers in the basic computer is controlled by a master clock generator. The clock pulses are applied to all flip-flops and registers in the system, including the flip-flops and registers in the control unit. The clock pulses do not change the state of a register unless the register is enabled by a control signal. The control signals are generated in the control unit and provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and microoperations for the accumulator.
There are two major types of control organization:
- hardwired control and
- microprogrammed control.
In the hardwired organization, the control logic is implemented with gates, flip-flops, decoders, and other digital circuits. It has the advantage that it can be optimized to produce a fast mode of operation. In the microprogrammed organization, the control information is stored in a control memory. The control memory is programmed to initiate the required sequence of microoperations. A hardwired control, as the name implies, requires changes in the wiring among the various components if the design has to be modified or changed.
In the microprogrammed control, any required changes or modifications can be done by updating the microprogram in control memory.
The block diagram of the control unit is shown in Fig. 5.6.
It consists of two decoders,
- a sequence counter, and
- a number of control logic gates.
An instruction read from memory is placed in the instruction register (IR).position of this register in the common bus system is indicated in Fig 5.4.
The instruction register is shown again in Fig. 5.6, where it is divided into three parts:
- the 1 bit,
- the operation code, and
- bits 0 through 11.
The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The eight outputs of the decoder are designated by the symbols D0 through D7. The subscripted decimal number is equivalent to the binary value of the corresponding operation code. Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I. Bits 0 through 11 are applied to the control logic gates. The 4-bit sequence counter can count in binary from 0 through 15. The outputs of the counter are decoded into 16 timing signals T0 through T15.
The sequence counter SC can be incremented or cleared synchronously. Most of the time, the counter is incremented to provide the sequence of timing signals out of the 4 x 16 decoder. Once in a while, the counter is cleared to 0, causing the next active timing signal to be T0.
As an example, consider the case where SC is incremented to provide timing signals T0, T1, T2, T3, and T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is active. This is expressed symbolically by the statement
D3T4: SC <__ 0
The timing diagram of Fig. 5-7 shows the time relationship of the control signals.
The sequence counter SC responds to the positive transition of the clock. Initially, the CLR input of SC is active. The first positive transition of the clock clears SC to 0, which in tum activates the timing signal T0 out of the decoder. T0 is active during one clock cycle. The positive clock transition labeled T0 in the dagram will trigger only those registers whose control inputs are transition, to timing signal T0. SC is incremented with every positive clock transition unless its CLR input is active. This produces the sequence of timing signals T0, T1, T2, T3 ,T4 and so on, as shown in the dagram. (Note the the relationshuip between the timing signal and and its corresponding positive clock transition.) If SC is not cleared, the timing signals will continue with T5, T6 up to T15 and back to T0
The last three waveforms in Fig. 5-7 show how SC is cleared when D3T4 = 1. Output D3 from the operation decoder becomes active at the end of timing signal T2. When timing signal T4 becomes active, the output of the AND gate that implements the control function D3T4 becomes active. This signal is applied to the CLR input of SC. On the next positive clock transition (the one marked T4 in the diagram) the counter is cleared to 0. This causes the timing signal T0 to become active instead of T5 that would have been active if SC were incremented instead of cleared.
A memory read or write cycle will be initiated with the rising edge of a timing signal. It will be assumed that a memory cycle time is less than the clock cycle time. According to this assumption, a memory read or write cycle ini tiated by a timing signal will be completed by the time the next clock goes through its positive transition. The clock transition will then be used to load the memory word into a register. This timing relationship is not valid in many computers because the memory cycle time is usually longer than the processor clock cycle. In such a case it is necessary to provide wait cycles in the processor until the memory word is available. To facilitate the presentation, we will assume that a wait period is not necessary in the basic computer.
To fully comprehend the operation of the computer, it is crucial that one understands the timing relationship between the clock transition and the timing signals. For example, the register transfer statement
T0: AR <__ PC
specifies a transfer of the content of PC into AR if timing signal T0 is active. T0 is active during an entire clock cycle intervaL During this time the content of PC is placed onto the bus (with S2S1S0 = 010) and the LD (load) input of AR is enabled. The actual transfer does not occur until the end of the clock cycle when the clock goes through a positive transition. This same positive clock transition increments the sequence counter SC from 0000 to 0001 . The next clock cycle has T1 active and T0 inactive.
Frequently Asked Questions
- DATA TYPES
- NUMBER SYSTEM
- CONVERSION - INTRODUCTION
- OCTAL AND HEXADECIMAL NUMBER CONVERSION
- OCTAL AND HEXADECIMAL NUMBER CONVERSION -2
- Introduction to Decimal Representation
- ALPHANUMERIC REPRESENTATION
- Complements -2
- Subtraction of Unsigned Numbers
- Subtraction of Unsigned Numbers-2
- Fixed-Point Representation
- Integer Representation
- Arithmetic Addition
- ARITHMETIC SUBTRACTION